发明名称 PULSE OUTPUT CIRCUIT
摘要 PURPOSE:To prevent a step from being caused to the leading/trailing of an output pulse signal by eliminating the timing deviation of the conduction/ nonconduction of each transistor (TR) constituting a pulse output circuit. CONSTITUTION:When an L level pulse is fed to an input terminal 1, TRs Q1, Q2, Q4 and Q5 are turned off and a TR Q3 is turned on and a current flowing through a TR Q3 is fed from an output terminal 2 to an external load 3. In case an H level pulse is fed to the input terminal 1, the operation is conversed from above, and a voltage at the output terminal 2 goes to an L level. In the operation above, the current change of the TRs Q2, Q5 is changed at the same time. Thus, the pulse signal appearing at the output terminal 2 has no step at the leading and trailing.
申请公布号 JPS62220025(A) 申请公布日期 1987.09.28
申请号 JP19860063782 申请日期 1986.03.20
申请人 VICTOR CO OF JAPAN LTD 发明人 IWASHIMA MAKOTO;HAYAKAWA MITSURU
分类号 H03K17/60;H03K17/62;H03K19/088 主分类号 H03K17/60
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