发明名称 SUPPRESSING CIRCUIT FOR GENERATION OF GLITCH OF DIGITAL-ANALOG CONVERTER
摘要 PURPOSE:To suppres effectively generation of glitch by providing always a DC voltage and a required bias voltage to a digital input of a D/A converter by the 1st and 2nd division resistors. CONSTITUTION:The 1st resistor R1 (several hundred ohms) is inserted to a line connecting a switch means S10 and a switching circuit S1. The connecting point between the resistor R1 and the switching circuit S1 is connected to a DC positive voltage Vb of +10V by the 2nd resistor R2 of several hundred ohms. In selecting properly the DC voltage Vb and the resistors R1, R2, the leading edge/trailing edge characteristics of the switching circuit S1 and the threshold voltage Vt are selected as shown in figure. Thus, the generation of glitch based on the switching characteristic of a DAC is suppressed. In such a case, the 1st resistor R1 forms a time constant circuit together with the stray capacitance in the circuit and the effect to bring the trailing edge characteristic close to the leading edge characteristic more or less is provided.
申请公布号 JPS62219819(A) 申请公布日期 1987.09.28
申请号 JP19860062592 申请日期 1986.03.20
申请人 NAKAMICHI CORP 发明人 KOBAYASHI KOZO
分类号 H03M1/08;H03M1/00 主分类号 H03M1/08
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