| 摘要 |
PURPOSE:To control the phase of a clock so as to be an optimum phase by measuring time between the polarity transition point of an output from a voltage comparator comparing a demodulated output voltage with a reference voltage and the clock and setting up said time to a half of a clock period. CONSTITUTION:An output from a demodulating circuit 1 demodulating a modulated signal is compared with the reference voltage by the voltage comparator 2 and the output of the comparator 2 is inputted to an FF3 constituting an instantaneous polarity deciding circuit. The phase of a clock reproduced from the demodulated signal by a clock reproducing circuit 4 is adjusted by a phase shifting circuit 5 and inputted to a clock terminal C of the FF3. The outputs of the circuits 2 and 5 are inputted to a control circuit 6. When a DF1 and a DF2 of D-type FFs output pulses having the width obtained by measuring the time between a transition point from negative polarity to positive polarity of the output of the circuit 2 and the clock and the time between a transition point from the positive polarity to the negative polarity and the clock and a DF3 outputs a pulse having the width of a clock period, the set outputs of the DF1 and DF2 become the time width corresponding to a half of the clock period. The circuit 5 is controlled by a signal having the time width through an operation amplifier OPA to control the clock phase automatically so as to be an optimum phase. |
