| 摘要 |
PURPOSE:To transfer stack data at a high speed by detecting the final stage where data is stacked and transferring data to be stacked next from a data bus directly to the stage right before the final stage. CONSTITUTION:A selector 14 is enabled to connect the data bus 3 directly to a data latch 11 of each stage. Consequently, data to be stacked is stacked in a desired data latch speedily. The data latch where the data is stacked is the data latch right before the final stage of the data latch which has effective data and detected from the set/reset state of a flag latch 12. For example, it is detected by a final stage detection part 5 composed of an AND circuit and data can be stacked in the data latch right before the final stage by jumping over data latches in the middle, so the time required for the transfer is shortened, an output-side wait time is shortened, and fast processing is performed.
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