| 摘要 |
<p>PURPOSE:To increase the capacity of a semiconductor integrated circuit device by providing a gate electrode for information writing or erasure nearby a floating gate electrode and thus constituting a field-effect transistor (memory cell), and connecting field-effect transistors (FET) in series and thus constituting a memory cell array. CONSTITUTION:A memory cell of an EPROM consists of an FET Q which has a floating gate electrode, a control gate electrode, and a gate electrode for information writing. Then, FETs Q11-Qn1, Q12-Qn2,... arranged in rows have their source or drain areas connected adjacent drain or source areas respectively. Namely, the FETs Q11-Qn1, Q12-Qn2,... constitute a longitudinal type memory cell row connected in series by the specific number of bits (e.g. 8, 16, 32...) in the row direction. Plural memory cell rows are arranged in a matrix to constitute the memory cell array.</p> |
