| 摘要 |
PURPOSE:To reduce the gate parasitic capacity while shortening the gate length by a method wherein a sidewall pattern comprising an insulating layer is formed on the sidewalls of a recession formed in a base and then a gate electrode is formed in the recession. CONSTITUTION:A source electrode 3, a drain electrode 4 and the first insulating layer 5 are formed on a base comprising a substrate 1 with a cap layer 2 deposited thereon. First, an opening 7 is made in the insulating layer 5 using a resist film 6 with an opening pattern made therein further to etch the cap layer 2 using the insulating layer 5 as a mask. Second, after forming the second this insulating layer 8, the base 1 is exposed by directional etching process simultaneously to form sidewall pattern on sidewalls of recession. Successively after coating overall surface with an Al layer to form a gate electrode pattern on the recession, the resist film 6 and the Al layer 9 coated thereon are removed to manufacture a FET. Through these procedures, the gate parasitic capacity can be reduced while shortening the gate length.
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