| 摘要 |
PURPOSE:To attain the same test as a conventional test to be put to a pin and to obtain CMOS connection logic for mutual optional pins by providing two control signals controlling the output state of a tri-state gate and an output enable control circuit. CONSTITUTION:The state of the tri-state output gate 6 is controlled by an output signal 10 of a control FF 13 at normal operation. In the test of a CMOS integrated circuit 1, state control signals 8, 9 control the output state of the gate 6. When the signal 8 is logic '1', the gate 6 is made ineffective by an AND gate 11 and the output has a high impedance. In bringing the signal 8 to logic '0' and the signal 9 to logic '1', the gate 6 is made effective by an OR gate 12, and the output goes to low or high level depending on the value of the FF 13 and the gate is tested as a conventional output gate.
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