发明名称 PHASE LOCKED LOOP CIRCUIT
摘要 PURPOSE:To decide a synchronizing/asynchronizing state without any error even with a discrete input signal by using a sampling type loop filter and a sampling type low-pass filter in place of a conventional loop filter and low pass filter. CONSTITUTION:The sampling type low-pass filter 22 applies sampling filtering during a period when an input signal Sin exists and keeps the state just before while the input signal Sin does not exist. A conventional loop filter is used as the sampling loop filter 21 corresponding to the sampling low-pass filter 22, applies the filtering for a prescribed period only the same as the filter 22 and the state just before is kept as it is at no signal. As a result, a synchronizing detection signal Sdet is obtained independently of the time rate of the presence and absence of the input signal Sin.
申请公布号 JPS62216527(A) 申请公布日期 1987.09.24
申请号 JP19860058221 申请日期 1986.03.18
申请人 FUJITSU LTD 发明人 MISHIRO TOKIHIRO
分类号 H03L7/095;H03L7/08 主分类号 H03L7/095
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