发明名称 FACSIMILE RECEIVER
摘要 PURPOSE:To freely execute the timing control of a driving system and a printing by providing a line memory between a decoding part and a thermal head control circuit and controlling the writing and reading. CONSTITUTION:Receiving data at every line are decoded by a decoder 2, and accumulated in a line memory 4. When the decoding of one line is completed, simultaneously when a control part 1 generates a driving signal 23 to the recording scanning system, picture signal data 22 by one line are transferred from the memory 4 to shift register 6 of a thermal head control circuit 5. Since the transfer is executed during the decoding of the next line, the address designation of the memory 4 is executed by changing it over for reading and for writing by the logic of a transfer clock. For such a reason, for the memory 4, the same two memories are connected in parallel and the reading and writing are alternately executed. After the motor is driven and the delaying is executed corresponding to the communication delaying, the data of one line are latched from the register 6 to a data latch circuit 7 by a latch signal 24 from the control part 1. Thus, the timing control of a paper sending and a printing can be executed by the signal 24.
申请公布号 JPS62216585(A) 申请公布日期 1987.09.24
申请号 JP19860061424 申请日期 1986.03.18
申请人 NEC CORP 发明人 SUGIO TORU;MATSUDA YUKIHIRO;FUNAHASHI AKINORI;WATANABE HIDEAKI
分类号 H04N1/032;H04N1/19;H04N1/40 主分类号 H04N1/032
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