发明名称 PHASE LOCKED LOOP CIRCUIT
摘要 PURPOSE:To decrease further the locking time of a variable frequency oscillator by using an analog switch to short-circuit an input of a series resistor of a loop filter and a dividing point of a divided damping resistor. CONSTITUTION:The loop filter 8 consists of a series resistor R1 and divided damping resistors R2, R3 and a capacitor C1. The analog switch S is connected between the input of the series resistor R1 and the dividing point of the damping resistors and when an output of a lock detector 7 detecting the synchronizing state of a phase comparator 1 is asynchronous, the analog switch S is closed. As a result, the phase comparator 1 and the buffer circuit 5 are connected by a synthesized resistor subjected to parallel connection of the resistors R1, R2. That is, the analog switch S is closed at the asynchronous state and the cut-off frequency of a low-pass filter is changed to 0.02Hz to reduce the locking time of a variable frequency oscillator 3 further than a conventional circuit.
申请公布号 JPS62216528(A) 申请公布日期 1987.09.24
申请号 JP19860061657 申请日期 1986.03.18
申请人 FUJITSU LTD 发明人 KIDENA MINORU
分类号 H03L7/107;H03L7/10 主分类号 H03L7/107
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