发明名称 MULTIPORT MEMORY CIRCUIT
摘要 PURPOSE:To secure the priority processing of a 1st-arrival port side at the time of selected address contention with a simple circuit constitution by holding the acceptance of access from other ports until the processing for the selected address of the 1st-arrival port is completed. CONSTITUTION:If the coincidence between address signals inputted to two ports is detected by a detection circuit 2 when the change of an address signal which is inputted to one port is detected by the change detecting circuit 3 of an address contention adjusting circuit 20, an FF circuit 4 takes out the detec tion signal of the circuit 2 based on the detection signal of the circuit 3. Then when a signal BUSY is outputted to an external circuit connected to the port whose change is detected, the acceptance of access is held until the processing of the same address from the other port is completed and when the signal BUSY is not outputted, the signal BUSY is outputted to an external circuit connected to the other port and the acceptance of access is held until the coinci dence of the address signal is reset.
申请公布号 JPS62217481(A) 申请公布日期 1987.09.24
申请号 JP19860058225 申请日期 1986.03.18
申请人 FUJITSU LTD 发明人 AOYAMA KEIZO
分类号 G11C7/00;G11C8/00;G11C11/34;G11C11/41 主分类号 G11C7/00
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