发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 <p>PURPOSE:To smoothly deal with needs by selecting one of plural memory planes and switching access by a row or column scan optionally for the selected plane. CONSTITUTION:A row scanning decoding circuit 4 and a column scanning decoding circuit 5 select (n) memory cells in rows and columns specified based on an external address signal AD2 for an optional memory cell plane in a memory cell array 1 which has memory cell planes in (n) rows and (n) columns selected by a plane selecting circuit 2 with an external address signal AD1. Further, a switching circuit 5 selects the circuit 3 or 4 according to a specific signal level to select row or column units to be scanned for the selected memory cell plane.</p>
申请公布号 JPS62217489(A) 申请公布日期 1987.09.24
申请号 JP19860058211 申请日期 1986.03.18
申请人 FUJITSU LTD 发明人 KAWASHIMA SHOICHIRO
分类号 G11C7/00;G11C8/00;G11C11/34;G11C11/401;G11C11/413 主分类号 G11C7/00
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