| 摘要 |
PURPOSE:To execute the time base change correction without damaging the interleaving relation by dividing a memory having the memory capacity of one field into an N block, including a jitter by the high speed clock for generating a writing address to this and executing the correct clocking by the high speed clock for generating the reading address. CONSTITUTION:Respective memory parts 14-17 dividing a memory device having the memory capacity for one field into an N block (in the embodiment, N=4) receive successively the address designation by a writing address generating means at every horizontal period, and a digital video signal is written. A writing address generating means generates an address by using the high speed clock from a phase locking loop circuit 23 to phase-synchronize to a synchronizing signal recorded in the recording medium (tape). On the other hand, the data of respective memory parts are the phase different from the writing, and read successively by receiving the address designation from a reading address generating means at every horizontal period. The reading address generating means generates the address by using the high speed from a phase locking loop circuit 30 phase-synchronizing with a reference signal from the rotary system for recording and reproducing the recording medium.
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