Programmable sequencer.

摘要

A programmable sequencer (10) which uses an input mapping circuit (20) including a programmable logic array (30) to map decision variable input conditions onto branch address signals, which are used with primary address signals to form a next state address for state word memory (50). Input mapping circuit (20) preferably includes a branch control circuit (40), controlled by feedback signals from the output of state word memory (50), to selectively transform branch address signals to allow different states to use state word locations sharing the same primary address in state word memory (50). The preferred embodiment also includes a diagnostic circuit (80) useful for programming, and/or diagnosing operation of, sequencer (10).