发明名称 |
Logic analyzer |
摘要 |
Logic output data of a plurality of channels simultaneously obtained from a circuit under test are sequentially input in a memory, and after inputting a predetermined amount of such data, they are compared with corresponding expected values. The input data are divided into blocks, each including a plurality of data. Whether a mismatch is present in the comparison results for each block is indicated by a respective block element, and such block elements are displayed in a predetermined arrangement. It is also possible to provide a conventional list display including the input timing corresponding to the comparison results in which a mismatch is present.
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申请公布号 |
US4696004(A) |
申请公布日期 |
1987.09.22 |
申请号 |
US19850737466 |
申请日期 |
1985.05.24 |
申请人 |
TAKEDA RIKEN KOGYO KABUSHIKIKAISHA |
发明人 |
NAKAJIMA, TAKAYUKI;AOKI, TETSUO;KOBAYASHI, KATSUMI;AKIYAMA, NOBORU |
分类号 |
G01R31/3177;G06F11/25;(IPC1-7):G06F11/00 |
主分类号 |
G01R31/3177 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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