发明名称 Method of generating test patterns for logic network devices
摘要 Nodes and paths for connecting the nodes are used to form a model of at least one logic network. Next, all paths for connecting nodes in the logic network are traced, and the nodes and connecting path segments are sensitized and justified. The sensitizing patterns, when generating test patterns for a sequential circuit wherein the output is a function of a time sequence of inputs, may include a time sequence of sensitizing or input patterns for testing a single path through the network.
申请公布号 US4696006(A) 申请公布日期 1987.09.22
申请号 US19850802114 申请日期 1985.11.25
申请人 NEC CORPORATION 发明人 KAWAI, MASATO
分类号 H04L29/14;G01R31/28;G01R31/3183;G06F17/50;(IPC1-7):G01R31/28 主分类号 H04L29/14
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