| 摘要 |
PURPOSE:To decrease the area of a chip by connecting the output terminal of a flip-flop and a test mode input terminal disposed in the vicinity to reduce a wiring region. CONSTITUTION:A flip-flop F1 and a flip-flop F3 approaches on an LSI, and the flip-flop F3 and a flip-flop F2 approaches. Then, the output terminal Q of the flip-flop F1 is connected with the data input terminal TD of the flip-flop F3 by a connecting line l2, and the output terminal Q of the flip-flop F3 is connected by a connecting line l3 with the data input terminal TD of the flip- flop F2. An input terminal 21 is connected with the data input terminal TD of the flip-flop F1 by a connecting line l1, and the output terminal Q of the flip-flop 2 is connected by a connecting line l4 with other 2-port flip-flop on the LSI. Thus, the lines l1-l4 for scan pass test are not laid long nor crossed to eliminate an increase in the wiring region.
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