发明名称 MEMORY DEVICE
摘要 PURPOSE:To read the optional data out of a data register by providing a control means which presets the addresses excepting the read start address. CONSTITUTION:The preset data (initial values 10 and 137 of column address, initial value N of row address) is inputted to an address generating part A1. Thus a column address 10 is inputted to a column decoder 4 and a serial address counter 8 via an address buffer 3 together with a row address N inputted to a row decoder 5 respectively. Then the N-th line data of a memory cell array 1 are inputted to data registers 6A-6D. The counter 8 starts counting at and after 10 of the register shown by the count value to transfer it to a picture display device every 4 bits via a buffer 9. When the counter 8 counts up to 127, a column address 0 is outputted from an address generating part A2 by a pulse P1 received from a pulse generating part 10. Then the transfer is through with (4bitX128=512bit) when the value of the counter 8 reaches 9.
申请公布号 JPS62216056(A) 申请公布日期 1987.09.22
申请号 JP19860058386 申请日期 1986.03.18
申请人 TOSHIBA CORP 发明人 SHIMURA YASUSHI;ABE AKITATSU
分类号 G06F12/00;G06F12/02;G06T1/60;G11C11/401 主分类号 G06F12/00
代理机构 代理人
主权项
地址