发明名称 RECORD CONTROL SYSTEM FOR LOGICAL SIMULATION DEVICE
摘要 PURPOSE:To record a large quantity of simulation result at high speed by providing >=2 exclusive memories which record the simulation results to a logical simulation device containing plural processors that simulate logically the operations of devices and circuits and output these simulation results. CONSTITUTION:When the simulation results are outputted from processors 1-1-1-n, an output control part 15 detects these results and stores them in write address counter 11 for count-up operation. A selector 7 selects and uses an exclusive memory 2-1 and a comparator 9-1 compares the counter 11 with an end address register 10. Then a writing action is performed with control to the memory 2-1 by a write instruction given from a decoder 14 if no coincidence is obtained between the counter 11 and the register 10. If the coincidence is obtained between them, the comparator 9-1 sends the coincidence signal to a status register 13 to change the status information. Then the selector 7 switches an exclusive memory 2-2 in place of the busy memory 2-1 and continues the write control operation.
申请公布号 JPS62216046(A) 申请公布日期 1987.09.22
申请号 JP19860059676 申请日期 1986.03.17
申请人 FUJITSU LTD 发明人 MASUDA JUNICHI
分类号 G06F11/25;G06F11/26;G06F17/50 主分类号 G06F11/25
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