ARITHMETIC SYSTEM FOR FIXED DECIMAL POINT

摘要

PURPOSE:To improve the arithmetic accuracy for a fixed decimal point without increasing internal data length by storing some of those low-order bits to be omitted based on the result of multiplication into a register within a multiplier and adding these omitted bits to the low-order bits which are produced in the same way by the next multiplication. CONSTITUTION:The data read out of an input data buffer 1 is inputted to a fixed decimal point multiplier 3. In this case, the code of the input at a single side is inverted as necessary by a code inverter 2. Some of the low-order bits to be omitted by the result of multiplication are added to the contents of a register 4. The result of this addition is stored in the register 4 as it is. Then '1' is added to the high-order bit of said result of multiplication if the result of addition has an overflow. Thus the result of addition of '1' is outputted as the final result of multiplication and stored in an intermediate data buffer 5. Here the results of products are added together by a fixed decimal point adder 6. The flow of these data is controlled by a controller 7.