| 摘要 |
PURPOSE:To monitor the processing time accurately by counting busy signals of scalar and vector processors, the overall processing time, and the overlap time between both processors. CONSTITUTION:ORs among outputs of busy flip-flops 10 of a scalar processor 7 and busy flip flops 11 of a vector processor 1 are operated in OR gate circuits 30 and 31 respectively to obtain a scalar processor busy signal 34 and a vector processor busy signal 35. These signals 34 and 35 are supplied to OR and AND gate circuits 32 and 33 to generate an in-process display signal 12 and an overlap display signal 36, and signals 34, 35, 12, and 36 are clocked by a performance analyzer 14 to obtain data for performance evaluation of a program.
|
