| 摘要 |
PURPOSE:To perform a manufacturing process in higher yield while maintaining a parasitic electrostatic capacity small by reaching an electrode on an active layer on a semi-insulating substrate in line width of 1mum or shorter, and increasing the end line width of the electrode 2mum or longer on the substrate. CONSTITUTION:An etching boundary line 4 etched in a mesa shape and an active layer 2 in contact with the top of a mesa step, and an electrode 1 on a substrate 3 in contact with the bottom of the mesa step are formed. In this case, the electrode 1 is a gate electrode of an MES-FET to arrive at the substrate 3 at a line width of 1mum or shorter on the layer 2 and the line 4, and increased in the line width 2mum or longer under the mesa step, i.e., on the top of the substrate 3 as a terminal. Thus, when the size of the terminal is increased to 2mum or longer so that a protective film material is readily inserted. As a result, a fine electrode pattern can be protected sufficiently. Thus, the electrode having small line width can accurately be formed to improve the yield.
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