| 摘要 |
PURPOSE:To shorten the time required for instruction advance read and to increase the processing speed by transferring an address from a central processing unit to a main memory device only in case of execution of branch instructions and making it unnecessary to transfer the address at every time of data storage in an IBR storage circuit in the other cases. CONSTITUTION:When a branch instruction is executed by a central processing unit a, an ICR branch instruction signal line 16 from an ICR storage circuit 1 and an IBR empty signal line 13 from an IBR storage circuit 2 are made conductive, and an ICR transfer instruction signal line 10 from an IBR empty control circuit 9 is made conductive. Thus, a SUBICR storage instruction signal line 17 from an SUBICR control circuit 8 is made conductive, and the address outputted from the ICR storage circuit 1 to an address data bus signal line 12 is fetched into an SUBICR storage circuit 7. Next, a data read instruction signal line 18 is made conductive, and the address stored in the SUBICR storage circuit 7 is updated to read out data in a main memory device B.
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