| 摘要 |
PURPOSE:To quicken the read operation by connecting a MOSFET in parallel with a nonvolatile memory cell, conducting the FET for a prescribed time just after the write and discharging the remaining charge of a drain line of the nonvolatile memory cell. CONSTITUTION:A control signal the inverse of phi6 related to the write f a FAMOS 1 is inputted to a circuit 10. The circuit 10 uses CMOS inverters 11a-11e, gates 13a, 13b comprising CMOSFETs 12a, 12b and capacitive elements 14a-14d to retard the signal the inverse of phi6 by a prescribed time. The delayed control signal 17 is led to a 2-input CMOS NAND gate 16 together with the signal the inverse of phi6, the gate output 18 is inverted via a CMOS inverter 19, to turn on/off an N-channel CMOSFET 21. The drain of the FET 21 is connected to a line 9 and the source is connected to a low potential line 6, the drain line 9 of the memory cell 1 (N-channel FAMOSFET) is discharged to quicken the read just after write. |
