发明名称 CMOS VARIABLE DELAY LINE
摘要 PURPOSE:To increase the variable delay quantity per one stage of inverter by using two MOS transistor (TR) gates at the power supply side as a delay quantity control input so as to change the voltage of the control input. CONSTITUTION:When a voltage of a delay quantity control input 29 is increased a little and the voltage of a delay quantity control input 30 is decreased a little, a current of TRs 16, 19 is increased and the ON-resistance is decreased, then the delay quantity of an output 31 to an input 25 is reduced. When a voltage of the input 29 is increased a little and the voltage of the input 30 is decreased a little, the delay quantity is increased much by the opposite phenomenon. That is, in changing the voltage of the inputs 29, 30, the delay quantity of the inverter is changed. Since the ON-resisntace of the TR is decided by the ratio of the gate width to the gate length, the ratio is decreased to increase the variable delay quantity per one stage of the inverter.
申请公布号 JPS62214716(A) 申请公布日期 1987.09.21
申请号 JP19860057210 申请日期 1986.03.14
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 TAKEGUCHI YORIYASU;SENOO TAKANORI
分类号 H03K5/13;H03K5/133;H03K5/134 主分类号 H03K5/13
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