PROCESSOR HALT CONTROL SYSTEM

摘要

PURPOSE:To report halt to the external and set the halt time optionally by providing a halt circuit which generates a synchronizing signal to the external in accordance with a halt instruction and holds the halt time. CONSTITUTION:When the halt instruction is read out from an instruction ROM 11 to an instruction register 12, the load signal LD of an instruction decoding part 13 and the halt time Th of the instruction register 12 are loaded to a counter 60 to count a system clock SYCL. A synchronizing signal SYNC is given from a zero detecting part 61 to the instruction decoding part 13 and an internal bus 5 is released to inhibit the transmission of control signal. Since a gate 63 is closed by the synchronizing signal SYNC passing an inverter 62, the system clock SYCL is not inputted to a sequence control part 1 and a processor is stopped.