| 摘要 |
PURPOSE:To reduce the synchronizing lock time by applying serial/parallel conversion at a location of a pattern to be recognized as a synchronizing frame as to a sent bit string and applying pattern detection and comparison simultaneously so as to avoid the generation of pseudo synchronization. CONSTITUTION:At the time of a transmission signal is inputted to a reception signal applied terminal 1, a serial/parallel converter 2 separates it into the data of each phase. The data of '0' phase are fed to a specific pattern detector 3, since a pattern outputted from a register storing a frame synchronizing pattern is applied to the detector 3, a coincidence signal of the both patterns is obtained. An other-phase pattern comparator 4 compares data of the 1st-3rd phases at the same time and at the time of the respective phases are coincident with each other, a signal representing that they are all specific data is outputted. A synchronizing signal detection circuit 5, at the time of both outputs of the detector 3 and the comparator 4 are normal, uses a synchronizing protection circuit 6 to check a prescribed number of times as the normal synchronizing pattern detection and outputs a frame synchronizing signal from a terminal 7. |
