| 摘要 |
PURPOSE:To simplify the constitution of a decoder for an error correction code whose low-order m-bit is (m+1)-bit by using a signal point coordinate where a high-order 4-bit depends on a low-order 3-bit. CONSTITUTION:A received signal is divided into a high-order (R-m)-bit and a low-order (m+l)-bit and they are stored respectively in ROMs 41, 42. The low-order bit is decoded by a low-order bit decoder 44, and a high-order bit is decoded by using a signal via a RAM 43 as a delay element and a decoding signal of a low-order bit at a memory 45 storing the information to decode the high-order bit and a logic circuit based on the signal coordinate point arrangement where the high-order bit is ruled by the low-order bit. Thus, the error correction code is decoded by the decoder for the low-order bit and the high-order bit to simplify the constitution of the decoder.
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