| 摘要 |
PURPOSE:To prevent the occurrence of a punch-through phenomenon between capacitor passive elements as well as to contrive accomplishment of high integration by a method wherein a memory cell 3 is arranged three-dimensionally in a highly efficient manner. CONSTITUTION:A semiconductor element, consisting of a gate 105 and a source 104, is provided on a substrate 101, and the first semiconductor layer 102a and the second semiconductor layer 102b are formed on the above-mentioned semiconductor element through the intermediary of insulating films 106 and 106a. A one transistor/one capacitor memory cell is formed on said semiconductor layers. To be more precise, a transfer gate metal oxide semiconductor field effect transistor (MOSFET), consisting of a gate insulating film 103a, a source and drain diffusion layer 104a and a gate electrode 105a, is formed in the first layer of semiconductor layer 102a, and a vertical type memory cell, consisting of a low impurity density layer 107a, a thin insulating layer 109a and a cell-plate electrode 110, is formed. A transfer gate MOSFET and a vertical type memory cell are formed in the second layer of semiconductor layer 102b in the same manner as above-mentioned. |
