Buffer circuit for integrated circuit.

摘要

n the buffer circuit (B) for an integrated circuit according to this invention a load MOS transistor (Q1) and a drive MOS transistor (Q2) are connected in series between a power source potential node (Vcc') and a ground potential node (Vss') of the integrated circuit. A constant current circuit means (Q3) is connected in series with a circuit including the load MOS transistor (Q1) and the drive MOS transistor (Q2).