TTL to CMOS logic level input buffer

摘要

A TTL to CMOS input buffer which prevents static current flow when the TTL input signal is in a relatively low voltage logic "1" state. A transition detector 44 responsive to the input TTL logic signal and a voltage boosting circuit 50 connected between a positive power supply VDD and the input to a first CMOS inverter 30 are utilized to sense an input signal transition from "0" to "1" and boost the TTL logic "1" signal to a voltage level that prevents the p-channel transistor 32 included in the CMOS inverter from turning "on". The voltage boosting circuit is subsequently disconnected from the input to the p-channel transistor to prevent the input from being fully charged to the positive power supply. <IMAGE>