| 摘要 |
PURPOSE:To make it possible to provide an interconnecting method for a semiconductor integrated circuit characterized by a high probability of layout of a gate array having a high yield rate and high reliability and easy implementation, by using a second layer interconnection for the interconnection among functional cells of this three-layer interconnection gate array at an interconnecting part, which is in parallel with the column of input/output terminals, using a third layer interconnection for an interconnection part, which is vertical to the column of the input/output terminals, thereby increasing the second layer interconnections more than the third layer interconnections. CONSTITUTION:In interconnection among functional cells 3, a third interconnection 4 is wired at an interconnection part, which is vertical to the column of input/output terminals 2. Second interconnections 3 are provided at an interconnecting part, which is in parallel to the column of the input/output terminals. Namely, a rectangular interconnecting region 12 for its exclusive use, which is long in parallel with the column of the input/output terminals, is provided between the column of the basic cells in a two-layer interconnection gate array. In this three- layer interconnection gate array, the interconnection part, which is vertical to the column of the input/output terminal, is made shorter than the parallel interconnection part. Thus the total interconnection wire length of the interconnection part, which is in parallel to the column of the input/output terminals, is longer than the total interconnection wire length, which is vertical to the column of the input/output terminals. |
