| 摘要 |
PURPOSE:To form an analog test system capable of responding to respective types of the device easily by giving the value of the converting start of a start address register and the converting end of a stop address register to an up-down counter as a data selecting signal and counting a clock for counting. CONSTITUTION:An up-down counter increases a counting value for a clock ck for one counting one by one, a data selector 21 makes the contents of the supplied counting value into a selecting signal and determines data BIT of converted parallel data PD outputted from a serial data output edge Q. For example, when the selecting signal at the time of the starting of conversion is 2, a Bit 2 of the converted parallel data PD given to a parallel data third input edge P3 is outputted. As the counting of the up-down counter proceeds, Bit 4 and Bit 5 are outputted. When the counting output of an up-down counter 22 comes to be 6, a comparator 28, to which the counting value of 6 is supplied, detects the coincidence of a value 6 of the end of the conversion of a stop address register 27, and supplies a parallel serial converting completing signal to a flip-flop circuit 25. |
