SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

摘要

PURPOSE:To suppress the difference of variation of delay times of two input timing signals and to attain sure timing comparison by constituting plural inverter circuits of a delay circuit by MOSFET of the same structure as a clocked inverter circuit applying timing comparison substantially. CONSTITUTION:A timing signal phi1 corresponding to an internal write enable signal WE is inverted by an input inverter circuit comprising MOSFETs Q51-Q54 and inputted to one clocked inverter circuit N10 applying substantial timing comparison. Further, a timing signal phi2 corresponding to an internal column address strobe signal CAS is inputted to the 1st stage inverter circuit of a delay circuit comprising MOSFETs Q61-Q64. Three inverter circuits of the similar constitution are connected to the post-stage of the inverter circuit and the delayed timing phi2 is fed to a node (na). The clocked inverter circuits N10, N11 are operated by the delayed signal phi2 in the node (na) and its inverted signal formed by the inverter circuit N1.