| 摘要 |
A method and apparatus for simulating a network comprising a plurality of processing elements useful in simulating, for example, complex digital combinatorial electronic logic circuits. Each type of digital logic element is assigned a symbol, and the symbols are stored in an array pattern in a memory, with the row and column addresses of the symbols in memory corresponding to their position in the network. The simulator sequentially retrieves each element in the network starting from an input and determines the element response to an input signal based on the type of element and the signals input to it. After all of the elements in the network have been processed, the simulated output of the network is available at the network output elements.
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