| 发明名称 |
CMOS CIRCUIT HAVING A REDUCED TENDENCY TO LATCH |
| 摘要 |
<p>The tendency of a CMOS circuit to latch up is reduced by implanting ions of germanium or tin into the source and drain regions of the circuit. The low energy gap of these ions lowers the band gap of the source and drain regions, which in turn inhibits their ability to inject tarriers into the substrate and well.</p> |
| 申请公布号 |
CA1226965(A) |
申请公布日期 |
1987.09.15 |
| 申请号 |
CA19850490092 |
申请日期 |
1985.09.05 |
| 申请人 |
FAIRCHILD CAMERA AND INSTRUMENT CORPORATION |
发明人 |
STRAIN, ROBERT |
| 分类号 |
H01L27/08;H01L21/265;H01L21/8234;H01L27/088;H01L27/092;H01L29/08;H01L29/167;H01L29/78;(IPC1-7):H01L29/16 |
主分类号 |
H01L27/08 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
|
| 地址 |
|
