| 摘要 |
PURPOSE:To speed up a FIFO and to obtain large-capacity by using a shift register or a memory cell array as a memory and using a shift register for write/read of data. CONSTITUTION:A prescribed value is set to a read position selecting shift register SR 11. When data is read out, the value in the SR 11 is shifted left by one bit in accordance with a signal R, and '0' is inputted to the right end. In case of data write, data in each column of an SR 12 for data storage is shifted right by one bit in accordance with a signal W and new data is written in the left end, and contents of the SR 11 are shifted right by one bit and '0' is inputted to the left end. Data in an SR cell SRC is shifted by a clock SCLK; and when '1' is given to a line 13, data of the SRC is outputted through a bus DB.
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