| 摘要 |
PURPOSE:To prevent the voltage withstanding capability of a cell transistor source/drain junction from lowering by a method wherein the upper end of a counter electrode is positioned lower than and separated from the source/drain region of the cell transistor and an insulating layer is provided to occupy the gap thus created. CONSTITUTION:A groove 4 runs inward from the surface of a semiconductor substrate 1 of one conductivity type and a first conductive layer 5 of the same conductivity type, coating the inside walls of the groove 4, serves as a counter electrode for a capacitor. A second conductive layer 7 of the opposite conductivity type is formed through the intermediary of a dielectric layer 6 and fills up the groove 4, and serves as a storage capacitor accumulating electrode. The upper end of the first conductive layer 5 in such a storage capacitor is positioned lower than the bottoms of the source/drain regions 9A and 9B of a MIS transistor, and a gap is provided between the first conductive layer 5 and the bottoms of the source/drain regions 9A and 9B. Further, if required, an insulating layer 8 is provided in the gap thus created. This design prevents the voltage withstanding capability of a source/drain junction from lowering. |
