发明名称 ARITHMETIC PROCESSING UNIT
摘要 PURPOSE:To use the most of an arithmetic unit for the operation of variable length data and fixed length data of an exponential part in common and to make the mixture of operation of both the data in the same program possible by converting the variable length data into the fixed length data to operate the data prior to the operation of the variable length data. CONSTITUTION:When an instruction group read out from a memory 50 is set up in an instruction buffer 101 and one instruction out of the instruction group is fetched in an instruction register 102 and decoded by a decoder 103, operation for fixed length data or variable length data is discriminated. When the discriminated result is indicated on a floating point arithmetic processor 200 by using a line L100, both the operations can be indipendently executed. Prior to the operation of both the floating point data, the data re converted into common exponential part fixed length floating point data on the basis of the operation discriminating result and the common exponential part fixed length floating point data of the operated result are converted into either one of both the floating point data.
申请公布号 JPS62208126(A) 申请公布日期 1987.09.12
申请号 JP19860050364 申请日期 1986.03.10
申请人 HITACHI LTD 发明人 NAGASAKA MITSURU;OMODA KOICHIRO
分类号 G06F7/485;G06F7/487;G06F7/50;G06F7/508;G06F7/52 主分类号 G06F7/485
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