| 摘要 |
PURPOSE:To simplify a manufacturing process, and to narrow isolation width by forming first layer poly Si onto a base body to shape MOS structure, isolating two regions holding MOS structure by applying constant voltage and forming an MOSFET element through self-alignment by using second layer poly Si. CONSTITUTION:A p<-> type well 1 formed to the surface of a semiconductor base body 5 consisting of an n<-> type Si single crystal, an oxide film (an SiO2 film) 6 and a poly Si film 7 as a first layer polycrystalline silicon layer for isolating an element are each shaped. An insulating gate 3 composed of body Si as a second layer polycrystalline silicon layer and source-drain sections 4 as impurity introducing regions are formed by n<+> diffusion layers. A p<+> layer is induced in an Si surface by applying negative voltage to the poly Si film 7 in MOS structure consisting of the poly Si film 7, the oxide film 6 and the p<-> well (an Si substrate), and the p<+> layer has action in which it electrically isolates a section between the oxide film 6 and the n-type substrate, thus displaying the effect of isolation by isolation width (d2) narrower than a conventional LOCOS or the like. |
