| 摘要 |
PURPOSE:To eliminate the deterioration in FET characteristics caused by fining, and to facilitate a change into an integrated circuit by forming a p-type layer only on the side walls of source-drain regions in the lower section of an operating layer. CONSTITUTION:Si ions are implanted to a semi-insulating GaAs substrate 1 to shape an n-type operating layer 12. A WN film is formed onto the operating layer 12, and a mask 19 for shaping a gate electrode is formed by an SiO2 film. The WN film 13 is processed by using the SiO2 film 19. n<+> type source- drain regions are shaped, leaving the SiO2 mask 19. The SiO2 film 19 as the upper layer of the gate electrode is removed, and p-type layers 14 are formed on the side walls of the source-drain n<+> regions 15, 16 and the lower section of the operating layer 12 through ion implantation, employing the gate electrode 13 as a mask. Accordingly, a short channel effect can be prevented by a simple process, and capacitance resulting in trouble on the high-speed operation of an FET can be reduced.
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