发明名称 GAAS INTEGRATED CIRCUIT
摘要 PURPOSE:To increase threshold voltage on the negative side, to improve drive capacitance and to compact I/O size and reduce chip size by implanting ions for forming an active layer in an E.FET for an I/O circuit and for shaping an active layer in a D.FET for a load FET through double ion implantation. CONSTITUTION:There are three kinds of threshold voltage (VTE) for an E.FET (12) for a DCFL, (VTD1) for a load FET for the DCFL and (VTD2) for a D.FET for an I/O circuit. Active layers in the FETs are shaped by implanting ions to a semi-insulating GaAs substrate. Threshold voltage is determined by the conditions (the dosage of ions and injection energy) of formation of the active layers. Consequently, the active layers are formed at the same time as the formation of the E.FET and the load FET-that is, both double ions implantation is performed-in the D.FET. Accordingly, the threshold voltage of the FET constituting the I/O circuit is set on the negative side from that of the FET organizing an internal circuit, thus largely reducing chip size.
申请公布号 JPS62206871(A) 申请公布日期 1987.09.11
申请号 JP19860048649 申请日期 1986.03.07
申请人 TOSHIBA CORP 发明人 KAWAHISA KATSUE;KAMEYAMA ATSUSHI;IGAWA YASUO
分类号 H01L27/095;H01L21/822;H01L21/8222;H01L27/04;H01L27/06;H01L27/082 主分类号 H01L27/095
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