发明名称 TROUBLE DETECTING CIRCUIT FOR ADDER
摘要 PURPOSE:To contrive the diagnosis of an adder by providing the input selecting circuits to both inputs of the adder for test of this adder and supplying the output of a counter to said both inputs of the adder to perform comparison between the output of the adder and the value obtained by doubling the output of counter. CONSTITUTION:Both selecting circuits 21 and 22 are switched to check whether an adder has a trouble or not while the adder 5 is not used. Thus the output of a counter 1 is sent to both inputs of the adder 5. The output of the counter 1 is doubled and delivered through a 1-bit left shifter 3. Here the output of the adder 5 must be double as much as the output of the counter 1 as long as the working of the adder 5 is normal. Then the output of the adder 5 must be equal to the output of the shifter 3. Thus it is possible to diagnose the adder 5 by comparing both outputs of the adder 5 and the shifter 3 through a comparator 4. The counter 1 is actuated by the clock that is used also for the actuation of the adder 5.
申请公布号 JPS62206642(A) 申请公布日期 1987.09.11
申请号 JP19860049871 申请日期 1986.03.07
申请人 NEC CORP 发明人 KAGA TAKAHIKO
分类号 G06F7/499;G06F7/50;G06F11/22 主分类号 G06F7/499
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