| 摘要 |
PURPOSE:To count a signal even when an addition input and a subtraction input are given simultaneously by applying count based on other signal after one signal inputted earlier is counted. CONSTITUTION:An output of an off-delay circuit 10 is inputted to a reset terminal R2 of a flip-flop circuit 2 to bring an output Q2 to an L level. Then an output of a NAND circuit 4 goes to an H level and an output of an inverter circuit 6 goes to an L level. An output of the off-delay circuit 10 is given to a direction discrimiantion circuit 12 at the same time, the output goes to an L level and inputted to a U/D terminal of an addition/subtraction counter 14 to form a subtraction count command signal. Further, an output of an on-delay circuit 10 is inputted to an on-delay circuit 13 via an OR circuit 11 and an on-signal is given to a clock input terminal CK of the counter 14 after a prescribed time t1, the signal is subtracted and the count becomes (n) from a value (n+1). |
