| 摘要 |
PURPOSE:To improve the output frequency of a prescaler by providing a D flip-flop circuit between a control circuit and the prescaler to retard a modulus control signal up to the output of the prescaler. CONSTITUTION:The D flip-flop circuit delays a modulus control output M.C.1 from a control circuit 7 up to an output fc of the prescaler 4. A modulus control signal inputted to the prescaler 4 is delayed from M.C.1 to M.C.2 by the D flip-flop 8. Thus, the period T of the output fc of the prescaler 4 is expressed as T>=td3+td1 and T>=td4+td2. Since D flip-flop Delay times td3, td4 are far shorter than the delay time of counters 6, A6 incorporating many flip-flops in general, the application with shorter T, that is, higher fc than a conventional synthesizer is attained.
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