| 摘要 |
<p>PURPOSE:To suppress a non-maskable interrupting request until a prescribed processing execution is completed even when a non-maskable interrupting request signal is inputted immediately after resetting by providing plural interrupting control circuits and a means to suppress the output. CONSTITUTION:When a resetting signal is inputted to an interrupting control circuit 3, an FF 23 and an FF 24 are reset and an output Q comes to be a logic 0. Thus, the output of a non-maskable interrupting control circuit 21 and a maskable interrupting control circuit 22 is prohibited by AND gates 25 and 26. Even when a non-maskable interrupting request signal NMI is inputted immediately after the system resetting is executed by a resetting input signal, the non-maskable interrupting request can be prohibited until a signal EI to set the FF 23 and the FF 24 comes to be a logic 1. Consequently, after the processing to initialize a CPU is executed, by making a signal EI into the logic 1 from the CPU by the instruction, the original processing can be executed without fail without causing the run-away of the CPU at the time of return from an interrupting processing.</p> |
