| 摘要 |
A variable-length encoding device includes a shift register for converting a binary data string representing an audio signal into unit words of three 2-bit data (e.g., (1,1), (1,0), and (0,1) and two 3-bit data (e.g., (0,0,0) and (0,0,1). The 3-bit data words are obtained such that the remaining 2-bit data (i.e., (0,0)) is used as upper two bits of each of the resultant 3-bit data and is combined with each of the "1" and "0" data of the resultant 3-bit data. The output data words from the shift register are converted by a logic circuit to the corresponding code words in one-to-one correspondence. Each code word has a bit number twice that of the input data word. If a bit array (1,0,1) is included in the code word bit stream thus obtained, this bit array is further converted to (0,0,1). |
