发明名称 BRANCHING INSTRUCTION PROCESSING SYSTEM
摘要 PURPOSE:To decrease the number of the code of a program, to execute the action on a small memory and to optimize a branching instruction between modules by replacing a temporary branching instruction to the branching instruction of the length of the code of the length necessary at the time of linking modules. CONSTITUTION:To an assembler 1, a source module 2 of a user program is inputted and an object module 3 and a table 6 are outputted. At the table 6, a means to hold a module size, a means to hold a relative address from the head or the end of the module to which a branching instruction in the branching instruction between modules belongs and a label holding means are provided. By using these means, branching can be executed by the branching instruction having a short code length concerning the branching instruction all modules in a program, and then, the instruction can be optimized to the branching instruction having a short code length. Namely, by replacing a temporary branching instruction with the branching instruction of the code length of the length necessary at the time of linking the modules, the number of the code of the program is decreased and the action can be executed on a smaller memory.
申请公布号 JPS62205431(A) 申请公布日期 1987.09.10
申请号 JP19860048987 申请日期 1986.03.05
申请人 NEC CORP 发明人 OKUMURA MITSUKO
分类号 G06F9/32;G06F9/44;G06F9/45 主分类号 G06F9/32
代理机构 代理人
主权项
地址