| 摘要 |
PURPOSE:To prevent a latch up from occurring by preventing the insulation-isolating characteristics from deteriorating while restraining the base node voltage change of parasitic thyristor from occurring by a method wherein impurity regions in the impurity concentration two figures higher than that of a semiconductor substrate and a well region are provided on the interconnection layer insulation-isolating respective MOS transistors and respective boundaries between the semiconductor substrate and the well region. CONSTITUTION:Within a CMOS semiconductor device, polycrystalline interconnections 45-50 formed through the intermediary of a thin oxide film 13 are fixed to a field region at the same potential as that of an N-type semiconductor substrate 11 in a P-type channel MOS side region likewise at the same potential as that of a P-type well region 12 in an N-type channel MOS side region. Furthermore, in the boundary part on the P-type well region 12, N<+> type impurity regions 20, 21 in the concentration two figures higher than that of the N-type semiconductor substrate 11 and at the same potential as that of said substrate 11 are provided likewise in the boundary part on the N-type semiconductor substrate 11, P<+> type impurity regions 22, 23 in the concentration two figures higher than that of the P-type well region 12 and at the same potential as that of said well region 12 are provided. |
