| 摘要 |
PURPOSE:To eliminate larger jitter components by widening a period possible for transfer to a parallel/serial conversion circuit by serial/parallel conversion to (n) times to bring the amount of jitter correction to (n) times. CONSTITUTION:An output of the 1st clock generator 6 following up the jitter components is added to a shift register 16a as a shift pulse to store output data of an A/D converter 1. On the other hand, the 3rd frequency division circuit 14 inputting the 1st clock outputs a 1/16 frequency division pulse to the 1st latch circuit 16b and every time 16 A/D conversion data are stored in the register 16a, the data are latched. Thus, the permissible phase error between the 2nd VCO 11 and the 2nd clock generator 13 is + or -500nsec and the serial/parallel conversion circuit 16 consisting of the 1st shift register 16a and the 1st latch circuit 16b expands the permissible phase error of the 2nd clock. The output of the 1st latch 16b is subjected to jitter rejection by a parallel/serial conversion circuit 17.
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